1. Field of the Invention
The present invention relates to communications systems. Specifically, the present invention relates to resetting communications systems.
2. Description of the Related Art
A Conventional communication system includes a transmitting device and a receiving device. In some communication systems, the same device performs transmitting and receiving. For example, a router or a network switch may receive data on one interface and transmit data on a second interface. Individual streams of data are typically communicated between the transmitting device and the receiving device. With the advent of the Internet and the requirement for increased bandwidth, data is now transmitted in parallel, between communications devices.
Timing synchronization between transmitter and receiver is required to accomplish communication. Memories are typically used to synchronize data. Conventional communication systems include systems where the transmitter and receiver are based on the same clock and systems where the transmitter and receiver are based on different clocks (e.g. one in the transmitter and one in the receiver). In synchronous communication systems the transmitter and receiver are based on the same clock or timing information. In asynchronous communication systems the transmitter and receiver are based on different clocks. Therefore in asynchronous communications, the transmitter and receiver may have different time domains. As a result, there is a need to re-synchronize communicated data. A memory in the receiving device is often used for this purpose. The memory re-synchronizes the data. Typically the type of memory used, is called a First-in, First-out (FIFO) memory.
A FIFO memory synchronizes data by performing a number of functions. For example a FIFO memory stores and processes data in the order that the data is received. In a conventional FIFO memory data is written into a memory space based on a first time domain and data is read out of the memory space based on a second time domain.
An asynchronous FIFO memory may include two timing domains. One domain is based on the transmitter clock and the second domain is based on the receiver clock. Writing data into the FIFO is performed based on the transmitter clock and reading data out of the FIFO is based on the receiver clock. Pointers are used to identify a memory location, in the FIFO, where data will be written into and where data will be read. A write pointer identifies a memory location that data will be written into. A read pointer identifies a memory location that data will be read from. Both the write pointer and read pointer move sequentially through the FIFO memory based on the transmitter clock and the receiver clock, respectively. In a conventional FIFO, the write pointer is based on the transmitter (e.g. input) clock and the read pointer is based on the receiver (e.g. output) clock.
In conventional systems, techniques are implemented to ensure that the write pointer and read pointer work in a cooperative relationship. For example, forced spacing between the write pointer and the read pointer may be implemented or testing will be performed on a memory space, to ensure that the memory space is written to and read from, at the right time.
To coordinate reading and writing, the location of the write and read pointers must be known. In addition, the speed that the pointers sequentially step through the memory must be managed. A number of techniques have been developed to coordinate reading and writing in the memory space and to manage the speed that the pointers move through the memory. For example, special characters may be sent in a communicated bit stream. The special characters cause the write pointer to advance while the read pointer remains stationary. In an alternative technique, the write pointer and read pointer may be spaced so that they don't overlap during operation.
Although the foregoing techniques are applicable to individual communications links, a number of newer communication systems include multiple communication links (e.g. multiple channels, multiple lanes), each communicating information in parallel. In the new communication systems, data is simultaneously transmitted across each link. The data is striped across each of the links and then consolidated in a memory such as a FIFO memory, located in a receiver.
Several additional timing issues result from communicating information in parallel. In systems that transmit information in parallel, although each link is based on the same transmitter clock, the data transmitted on each link may arrive at the receiver out of phase. In addition, the transmitter clock is different from the receiver clock. Lastly, intermediate communicating devices such as repeaters, may create further disparity between the data communicated on multiple parallel links. Ultimately, as a result of a combination of these effects, data communicated on different links may arrive in the receiver at different times. When data from different links arrives at the receiver at different times, the data is defined as skewed.
Skewed data causes many communications problems. For example, as a result of a mismatch between the read clock and the write clock, valid data may be incorrectly read from the FIFO storing the data. Data has to arrive at the FIFO before the write and read pointers begin to move through the FIFO. If data arrives on communication links at different (e.g. skewed) times, the pointers in each FIFO memory may move out of synchronization and move in an uncoordinated manner. For example, the data associated with one link may arrive in the FIFO and is ready to be read, however, the data associated with another link may not have arrived and is not available for reading. In this scenario, if information is read out of the FIFO, part of the information would be valid data, but part of the information may be invalid data (e.g. information associated with the second link).
In addition to the problems associated with aligning data and synchronizing data, a receiving system may stop operating or operate incorrectly as a result of the foregoing issues. In addition, simple operator error such as plugging cables into the wrong receptacle or improperly configuring the system may cause the system to incorrectly align or synchronize incoming data. When these issues occur, it is difficult to reconfigure the system. The system may hang or just continue to operate incorrectly.
Thus, in a scenario including several communications links, there is a need to coordinate data communicated across each link. There is a need to resynchronize data in a receiver. There is a need to coordinate writing data into a FIFO and reading data out of the FIFO when the writing is based on one time domain and the reading is based on a second, different time domain. There is a need to restart the system, so that the system does not hang or continue to operate incorrectly.